Urgent Segmented DAC design

[vsvamsi]

The design i have designed has in issue during the worst case transition that is from 0111 1111 to 1000 0000 .Can u please tell me how to rectify the glitch.The impedance of curent source very high. while observing the inputs of the switches of the current source that is the output of the D flip Flop is given to the input switch of current sources. I found the glitches which is generating the monotonicity issue.
Can u tell me how to rectify these glitches.